Datasheet

Section 7 Bus Controller
Page 172 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• Idle cycle insertion
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Write buffer functions
⎯ External write cycle and internal access can be executed in parallel
⎯ DMAC
*
single-address mode and internal access can be executed in parallel
• Bus arbitration function
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC
*
and DTC
*
• Other features
⎯ Refresh counter
*
(refresh timer) can be used as an interval timer
⎯ External bus release function
Note: * This function is not available in the H8S/2695.