Datasheet

Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
Page 164 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
6.2.4 Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.2.5 Module Stop Control Register C (MSTPCRC)
7
MSTPC7
1
R/W
Bit :
Initial value :
R/W :
6
MSTPC6
1
R/W
5
MSTPC5
1
R/W
4
MSTPC4
1
R/W
3
MSTPC3
1
R/W
2
MSTPC2
1
R/W
1
MSTPC1
1
R/W
0
MSTPC0
1
R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus
cycle, and module stop mode is entered. Register read/write accesses are not possible in module
stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
Bit 4
MSTPC4 Description
0 PC break controller module stop mode is cleared
1 PC break controller module stop mode is set (Initial value)