Datasheet

Appendix B Internal I/O Register
R01UH0166EJ0600 Rev. 6.00 Page 1249 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
SMR3—Serial Mode Register 3
SMR4—Serial Mode Register 4
SMR0—Serial Mode Register 0
SMR1—Serial Mode Register 1
SMR2—Serial Mode Register 2
H'FDD0
H'FDD8
H'FF78
H'FF80
H'FF88
Smart Card
Interface
7
GM
0
R/W
6
BLK
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
BCP1
0
R/W
0
CKS0
0
R/W
2
BCP0
0
R/W
1
CKS1
0
R/W
Note: Set bit 5 to 1 when using the smart card interface.
GSM Mode
0 Operation in normal smart card interface mode
(1) TEND flag set 12.5etu (11.5etu in block transfer mode) after start of first bit;
(2) ON/OFF control only of clock output.
1 Operation in GSM mode smart card interface mode
(1) TEND flag set 11.0etu after start of first bit;
(2) In addition to ON/OFF control of clock output, High/Low control also enabled (set by SCR).
Note: etu: Elementary time unit. The time to send 1 bit.
Block transfer mode
0 Operation of normal smart card interface mode
(1) Error signal output, detection, and automatic resending of data;
(2) TXI interrupt generated by TEND flag;
(3) TEND flag set 12.5etu after start of transmission (after 11.0etu in GSM mode).
1 Operation in block transfer mode
(1) No error signal output, detection, or automatic resending of data;
(2) TXI interrupt generated by TDRE flag;
(3) TEND flag set 11.5etu after start of transmission (after 11.0etu in GSM mode).
Basic clock pulse 1, 0
BCP1 BCP0
0 0 32 clock
1 64 clock
1 0 372 clock
1 256 clock
Bit
Initial value
R/W
:
:
: