Datasheet

Section 24 Power-Down Modes
R01UH0166EJ0600 Rev. 6.00 Page 1037 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 24.5 Oscillation Stabilization Time Settings
STS2 STS1 STS0
Standby
Time
25
MHz
20
MHz
16
MHz
12
MHz
10
MHz
8
MHz
6
MHz
4
MHz
2
MHz Unit
0 0 0 8192
states
0.32 0.41 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms
1 16384
states
0.65 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2
1 0 32768
states
1.3 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4
1 65536
states
2.6 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8
1 0 0 131072
states
5.2 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5
1 262144
states
10.4 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2
1 0 Reserved — — — — — — — — — µs
1 16 states
(Setting
prohibited)
0.6 0.8 1.0 1.3 1.6 2.0 1.7 4.0 8.0
: Recommended time setting
Using an External Clock: The PLL circuit requires a time for stabilization. Insert a wait of 2 ms
min.
24.6.4 Software Standby Mode Application Example
Figure 24.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.