Datasheet

Section 22 ROM
R01UH0166EJ0600 Rev. 6.00 Page 985 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
22.12 Flash Memory and Power-Down States
In addition to its normal operating state, the flash memory has power-down states in which power
consumption is reduced by halting part or all of the internal power supply circuitry.
There are three flash memory operating states:
(1) Normal operating mode: The flash memory can be read and written to.
(2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be
read when the H8S/2633 is operating on the subclock.
(3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or
written to.
States (2) and (3) are flash memory power-down states. Table 22.15 shows the correspondence
between the operating states of the H8S/2633 and the flash memory.
Table 22.15 Flash Memory Operating States
LSI Operating State Flash Memory Operating State
High-speed mode
Medium-speed mode
Sleep mode
Normal mode (read/write)
Subactive mode
Subsleep mode
When PDWND = 0: Power-down mode (read-only)
When PDWND = 1: Normal mode (read-only)
Watch mode
Software standby mode
Hardware standby mode
Standby mode
22.12.1 Note on Power-Down States
When the flash memory is in a power-down state, part or all of the internal power supply circuitry
is halted. Therefore, a power supply circuit stabilization period must be provided when returning
to normal operation. When the flash memory returns to its normal operating state from a power-
down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs
(power supply stabilization time), even if an oscillation stabilization period is not necessary.