Datasheet
Rev.6.00 Oct.28.2004 page 969 of 1016
REJ09B0138-0600H
R
P1nDDR
C
QD
Reset
WDDR1
Reset
WDR1
R
P1nDR
C
QD
P1
n
RDR1
RPOR1
Internal data bus
PPG module
TPU module
Pulse output enable
Output compare output/
PWM output enable
Output compare output/
PWM output
Pulse output
External clock input
Input capture input
WDDR1:
WDR1:
RDR1:
RPOR1:
n = 2, 3, 5, 7
Write to P1DDR
Write to P1DR
Read P1DR
Read port 1
Legend:
Figure C-1 (b) Port 1 Block Diagram (Pins P1
2
, P1
3
, P1
5
, and P1
7
)