Datasheet

Rev.6.00 Oct.28.2004 page 966 of 1016
REJ09B0138-0600H
TSR2—Timer Status Register 2 H'FFF5 TPU2
7
TCFD
1
R
6
—
1
—
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
—
0
—
0
TGFA
0
R/(W)*
2
—
0
—
1
TGFB
0
R/(W)*
0
1
TCNT counts down
TCNT counts up
Count Direction Flag
0
Underflow Flag
1
0
Overflow Flag
1
0
Input Capture/Output Compare Flag B
1
0 [Clearing conditions]
• When DTC is activated by TGIA interrupt
while DISEL bit of MRB in DTC is 0
• When DMAC is activated by TGIA interrupt
while DTA bit of DMABCR in DMAC is 1
• When 0 is written to TGFA after reading
TGFA = 1
Input Capture/Output Compare Flag A
1
Note: * Can only be written with 0 for flag clearing.
Bit
Initial value
Read/Write
:
:
:
[Setting conditions]
• When TCNT = TGRA while TGRA is
functioning as output compare register
• When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL
bit of MRB in DTC is 0
• When 0 is written to TGFB after reading
TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)