Datasheet

Rev.6.00 Oct.28.2004 page 962 of 1016
REJ09B0138-0600H
TGR1A—Timer General Register 1A H'FFE8 TPU1
TGR1B—Timer General Register 1B H'FFEA TPU1
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
8
1
R/W
10
1
R/W
9
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit
Initial value
Read/Write
:
:
:
TCR2—Timer Control Register 2 H'FFF0 TPU2
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
Counter Clear
0
1
0
1
0
1
0
1
Clock Edge
0
1
—*
Count at rising edge
Count at falling edge
Count at both edges
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on ø/1024
Time Prescaler
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7
—
0
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Note: This setting is ignored when channel 2 is in phase
counting mode.
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
Bit
Initial value
Read/Write
:
:
:
Note: * This setting is ignored when channel 2
is in phase counting mode.
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*