Datasheet

Rev.6.00 Oct.28.2004 page 883 of 1016
REJ09B0138-0600H
DMATCR—DMA Terminal Control Register H'FF01 DMAC
7
—
0
—
6
—
0
—
5
TEE1
0
R/W
4
TEE0
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
DMATCR
Initial value
Read/Write
:
:
:
:
Transfer End Enable 1
0
1
Transfer End Enable 0
0
1
TEND0 pin output disabled
TEND0 pin output enabled
TEND1 pin output disabled
TEND1 pin output enabled
DMACR0A—DMA Control Register 0A H'FF02 DMAC
DMACR0B—DMA Control Register 0B H'FF03 DMAC
DMACR1A—DMA Control Register 1A H'FF04 DMAC
DMACR1B—DMA Control Register 1B H'FF05 DMAC
15
DTSZ
0
R/W
14
SAID
0
R/W
13
SAIDE
0
R/W
12
BLKDIR
0
R/W
11
BLKE
0
R/W
8
—
0
R/W
10
—
0
R/W
9
—
0
R/W
0
1
Byte-size transfer
Word-size transfer
Data Transfer Size
0
1
Source Address Increment/Decrement
0
1
0
1
MARA is fixed
MARA is incremented after a data transfer
MARA is fixed
MARA is decremented after a data transfer
0
1
Block Direction/Block Enable
Reserved
Only 0 should be written to this bit.
0
1
0
1
Transfer in normal mode
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
Full address mode
Bit
DMACRA
Initial value
Read/Write
:
:
:
: