Datasheet

Rev.6.00 Oct.28.2004 page 875 of 1016
REJ09B0138-0600H
DRAMCR—DRAM Control Register H'FED7 Bus Controller
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Refresh Control
0
1
Refresh control is not performed
Refresh control is performed
RAS-CAS Wait
0 Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T
Rr
cycle
Refresh Mode
0
1
DRAM interface: CAS-before-RAS refreshing used
Self-refreshing used
Compare Match Flag
0
1
Cleared by reading the CMF flag when CMF = 1, then
writing 0 to the CMF flag
[Clearing condition]
[Setting condition]
Set when RTCNT = RTCOR
Compare Match Interrupt Enable
0
1
Interrupt request (CMI) by CMF flag disabled
Interrupt request (CMI) by CMF flag enabled
Refresh Counter Clock Select
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Count operation disabled
Count uses ø/2
Count uses ø/8
Count uses ø/32
Count uses ø/128
Count uses ø/512
Count uses ø/2048
Count uses ø/4096
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T
Rc1
cycle
1
RTCNT—Refresh Timer Counter H'FED8 Bus Controller
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Internal clock count value