Datasheet

Rev.6.00 Oct.28.2004 page 872 of 1016
REJ09B0138-0600H
BCRH—Bus Control Register H H'FED4 Bus Controller
7
ICIS1
1
R/W
6
ICIS0
1
R/W
5
BRSTRM
0
R/W
4
BRSTS1
1
R/W
3
BRSTS0
0
R/W
0
RMTS0
0
R/W
2
RMTS2
0
R/W
1
RMTS1
0
R/W
Bit
Initial value
Read/Write
:
:
:
Idle Cycle Insert 1
0
1
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Idle Cycle Insert 0
0
1
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
Area 0 Burst ROM Enable
0
1
Area 0 is basic bus interface
Area 0 is burst ROM interface
Burst Cycle Select 1
0
1
Burst cycle comprises 1 state
Burst cycle comprises 2 states
Burst Cycle Select 0
0
1
Max. 4 words in burst access
Max. 8 words in burst access
RAM Type Select
RMTS2
0
1
RMTS1
0
1
RMTS0
0
1
0
1
Area 5 Area 4 Area 3 Area 2
Normal space
DRAM
space
Normal space
DRAM space
Normal
space
DRAM space
Note: When areas selected in DRAM space
are all 8-bit space, the PF
2
pin can be
used as an I/O port, BREQO, or WAIT.