Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 128 (14x20) 16-Bit 20 MHz I/O number 87

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Rev.6.00 Oct.28.2004 page 848 of 1016

REJ09B0138-0600H

MRB—DTC Mode Register B H'F800—H'FBFF DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC Chain Transfer Enable

End of DTC data transfer

DTC chain transfer

DTC Interrupt Select

Reserved

Only 0 should be written to these bits

After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

After a data transfer ends, the CPU interrupt is enabled

SAR—DTC Source Address Register H'F800—H'FBFF DTC

Bit

Initial value

Read/Write

22 21 20 19 43210- - -

- - -

Specifies transfer data source address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

—————

DAR—DTC Destination Address Register H'F800—H'FBFF DTC

23Bit

Initial value

Read/Write

22 21 20 19 43210- - -

- - -

Specifies transfer data destination address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

CRA—DTC Transfer Count Register A H'F800—H'FBFF DTC

15Bit

Initial value

Read/Write

14 13 12 11109876543210

CRAH CRAL

Specifies the number of DTC data transfers

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

—————

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

—————

Unde-

fined

—