Datasheet

Rev.6.00 Oct.28.2004 page 810 of 1016
REJ09B0138-0600H
A.4 Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction execution by the CPU.
Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table
A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction
can be calculated from these two tables as follows:
Execution states = I × S
I
+ J × S
J
+ K × S
K
+ L × S
L
+ M × S
M
+ N × S
N
Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in
two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A-5:
I = L = 2, J = K = M = N = 0
From table A-4:
S
I
= 4, S
L
= 2
Number of states required for execution = 2 × 4 + 2 × 2 = 12
2. JSR @@30
From table A-5:
I = J = K = 2, L = M = N = 0
From table A-4:
S
I
= S
J
= S
K
= 4
Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24
Table A-4 Number of States per Cycle
Access Conditions
On-Chip Supporting
External Device
Module 8-Bit Bus 16-Bit Bus
Cycle
On-Chip
Memory
8-Bit
Bus
16-Bit
Bus
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch S
I
1 4 2 4 6 + 2m 2 3 + m
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 2 3 + m
Word data access S
M
4 4 6 + 2m
Internal operation S
N
11 1 1111
Legend:
m: Number of wait states inserted into external device access