Datasheet

Rev.6.00 Oct.28.2004 page 52 of 1016
REJ09B0138-0600H
Bus cycle
T
1
UnchangedAddress bus
AS
RD
HWR, LWR
Data bus
ø
High
High
High
Hi
g
h-impedance state
Figure 2-15 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the
particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules.
Figure 2-17 shows the pin states.
Bus cycle
T1 T2
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Internal address bus
ø
Figure 2-16 On-Chip Supporting Module Access Cycle