Datasheet

Rev.6.00 Oct.28.2004 page 734 of 1016
REJ09B0138-0600H
22.6.3 AC Characteristics
Figure 22-67 show, the test conditions for the AC characteristics.
C
LSI output pin
R
H
R
L
C = 90 pF: Ports 1, A to F
C = 30 pF: Ports 2, 3, 5, 6, G
R
L
= 2.4 k
R
H
= 12 k
I/O timing test levels
Low level: 0.8 V
High level: 2.0 V
5 V
Figure 22-67 Output Load Circuit
(1) Clock Timing
Table 22-26 lists the clock timing
Table 22-26 Clock Timing
Condition A: V
CC
= 2.7 to 5.5 V, AV
CC
= 2.7 to 5.5 V, V
ref
= 2.7 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 10 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition B: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 20 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition C: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, V
ref
= 3.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 13 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition A Condition B Condition C
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
Clock cycle time t
cyc
100 500 50 500 76 500 ns Figure 22-68
Clock high pulse width t
CH
35 20 23 ns
Clock low pulse width t
CL
35 20 23 ns
Clock rise time t
Cr
15 5 15 ns
Clock fall time t
Cf
15 5 15 ns
Clock oscillator setting
time at reset (crystal)
t
OSC1
20 10 20 ms Figure 22-69
Clock oscillator setting time
in software standby (crystal)
t
OSC2
20 10 20 ms Figure 21-2
External clock output
stabilization delay time
t
DEXT
500 500 500 µs Figure 22-69