Datasheet

Rev.6.00 Oct.28.2004 page 725 of 1016
REJ09B0138-0600H
Item Symbol Min Typ Max Unit
Test
Condition
Programming Wait time after SWE bit clear*
1
θ 100 — — µs
Maximum programming
count*
1
*
4
N — — 1000*
5
Times
Erase Wait time after SWE bit
setting*
1
x1——µs
Wait time after ESU bit
setting*
1
y 100 — — µs
Wait time after E bit setting*
1
*
6
z — — 10 ms Erase time
wait
Wait time after E bit clear*
1
α 10 — — µs
Wait time after ESU bit clear*
1
β 10 — — µs
Wait time after EV bit setting*
1
γ 20 — — µs
Wait time after H’FF dummy
write*
1
ε 2—— µs
Wait time after EV bit clear*
1
η 4—— µs
Wait time after SWE bit clear*
1
θ 100 — — µs
Maximum erase count*
1
*
6
N — — 100 Times
Notes: 1. Settings of each time must comply with algorithm of writing/erasing.
2. Writing time for 128 bytes: indicates the total period in which bit P of flash memory control register 1 (FLMCR1)
is set. Writing verification time is not included.
3. Erasing time for one block: indicates the period in which bit E of FLMCR1 is set. Erasing verification time is not
included.
4. Maximum writing time: t
P
(max) = Σ wait time (z) after setting of bit P
5. The maximum writing count (N) must be set to the maximum writing time (t
P
(max)) or less according the actual
set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n).
Writing count n
1 ≤ n ≤ 6 z = 30 µs
7 ≤ n ≤ 1000 z = 200 µs
[In additional writing]
Writing count n
1 ≤ n ≤ 6 z = 10 µs
6. Wait time (z) after setting of bit E and the maximum erasing count (N) have the following relationship to the
maximum erasing time (t
E
(max)).
t
E
(max) = wait time (z) after setting of bit E × maximum erasing count (N)