Datasheet

Rev.6.00 Oct.28.2004 page 720 of 1016
REJ09B0138-0600H
(5) Timing of On-Chip Supporting Modules
Table 22-18 lists the timing of on-chip supporting modules.
Table 22-18 Timing of On-Chip Supporting Modules
Conditions: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 10 to 20 MHz, T
a
= –20 to +75°C (regular specifications),
T
a
= –40 to +85°C (wide-range specifications)
Condition
Test
Item Symbol Min Max Unit Conditions
PORT Output data delay time t
PWD
— 50 ns Figure 22-54
Input data setup time t
PRS
30 —
Input data hold time t
PRH
30 —
PPG Pulse output delay time t
POD
— 50 ns Figure 22-55
TPU Timer output delay time t
TOCD
— 50 ns Figure 22-56
Timer input setup time t
TICS
30 —
Timer clock input setup
time
t
TCKS
30 — ns Figure 22-57
Timer clock
pulse width
Single
edge
t
TCKWH
1.5 — t
cyc
Both
edges
t
TCKWL
2.5 —
TMR Timer output delay time t
TMOD
— 50 ns Figure 22-58
Timer reset input setup
time
t
TMRS
30 — ns Figure 22-60
Timer clock input setup
time
t
TMCS
30 — ns Figure 22-59
Timer clock
pulse width
Single
edge
t
TMCWH
1.5 — t
cyc
Both
edges
t
TMCWL
2.5 —
SCI Input clock
cycle
Asynchro-
nous
t
Scyc
4—t
cyc
Figure 22-61
Synchro-
nous
6—
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5
Transmit data delay
time
t
TXD
— 50 ns Figure 22-62
Receive data setup
time (synchronous)
t
RXS
50 — ns
Receive data hold
time (synchronous)
t
RXH
50 — ns
A/D
con-
verter
Trigger input setup
time
t
TRGS
30 — ns Figure 22-63