Datasheet

Rev.6.00 Oct.28.2004 page 719 of 1016
REJ09B0138-0600H
ø
AS
A
23
to A
0
RD
(read)
CS7 to CS0
D
15
to D
0
(read)
HWR, LWR
(write)
D
15
to D
0
(write)
T
3
t
DACD1
T
2
t
DACD2
DACK0, DACK1
T
1
Figure 22-51 DMAC Single Address Transfer Timing (Three-State Access)
ø
TEND0, TEND1
t
TED
t
TED
T
1
T
2
or T
3
Figure 22-52 DMAC TEND Output Timing
ø
DREQ0, DREQ1
t
DRQH
t
DRQS
Figure 22-53 DMAC DREQ Intput Timing