Rev.6.00 Oct.28.2004 page 718 of 1016
REJ09B0138-0600H
ΓΈ
AS
A
23
to A
0
RD
(read)
CS7 to CS0
D
15
to D
0
(read)
HWR, LWR
(write)
D
15
to D
0
(write)
T
2
t
DACD1
T
1
t
DACD2
DACK0 , DACK1
Figure 22-50 DMAC Single Address Transfer Timing (Two-State Access)
