Datasheet

Rev.6.00 Oct.28.2004 page 692 of 1016
REJ09B0138-0600H
t
RDH
ø
T
C1
CAS
A
23
to A
0
t
ACC1
T
C2
t
AH
t
AS
t
CSD2
t
CSD3
t
ACC3
t
WRD2
t
WDD
t
WDH
CS5 to CS2
(RAS)
D
15
to D
0
(read)
HWR, LWR
(write)
D
15
to D
0
(write)
T
r
t
PCH
t
AD
t
CASD
t
ACC4
t
RDS
t
AD
t
CASD
t
WRD2
T
p
t
WCS
t
WDS
t
WCH
Figure 22-11 DRAM Bus Timing
ø
T
Rc1
CAS
T
Rc2
t
CASD
CS5 to CS2
(RAS)
T
Rr
t
CASD
t
CSD2
T
Rp
t
CSD1
t
CSR
Figure 22-12 CAS-Before-RAS Refresh Timing