Datasheet

Rev.6.00 Oct.28.2004 page 679 of 1016
REJ09B0138-0600H
21.8 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port.
When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is
enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, ø clock output is
disabled and input port mode is set. Table 21-5 shows the state of the ø pin in each processing state.
Table 21-5 ø Pin State in Each Processing State
DDR 0 1
PSTOP 0 1
Hardware standby mode High impedance
Software standby mode High impedance Fixed high
Sleep mode High impedance ø output Fixed high
Normal operating state High impedance ø output Fixed high