Datasheet

Rev.6.00 Oct.28.2004 page 671 of 1016
REJ09B0138-0600H
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2
SCK2
Bit 1
SCK1
Bit 0
SCK0 Description
0 0 0 Bus master in high-speed mode (Initial value)
1 Medium-speed clock is ø/2
1 0 Medium-speed clock is ø/4
1 Medium-speed clock is ø/8
1 0 0 Medium-speed clock is ø/16
1 Medium-speed clock is ø/32
1—
21.2.3 Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL
Bit :1514131211109876543210
Initial value : 0 0 1 1111111111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 21-3 for the method
of selecting on-chip supporting modules.
Bits 15 to 0
MSTP15 to MSTP0 Description
0 Module stop mode cleared
1 Module stop mode set