Datasheet

Rev.6.00 Oct.28.2004 page 665 of 1016
REJ09B0138-0600H
Table 20-4 and figure 20-6 show the input conditions for the external clock.
Table 20-4 External Clock Input Conditions
V
CC
= 2.7 V
to 5.5 V
V
CC
= 5.0 V ±
10%
Item Symbol Min Max Min Max Unit
Test
Conditions
External clock input
low pulse width
t
EXL
40 — 20 — ns Figure 20-6
External clock input
high pulse width
t
EXH
40 — 20 — ns
External clock rise time t
EXr
—10—5 ns
External clock fall time t
EXf
—10—5 ns
Clock low pulse width t
CL
0.4 0.6 0.4 0.6 t
cyc
ø ≥ 5 MHz Figure 22-4
level
80 — 80 — ns ø < 5 MHz
Clock high pulse width t
CH
0.4 0.6 0.4 0.6 t
cyc
ø ≥ 5 MHz
level
80 — 80 — ns ø < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 20-6 External Clock Input Timing
20.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal
from the oscillator to generate the system clock (ø).
20.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
20.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, or ø/8,
ø/16, and ø/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.