Datasheet

Rev.6.00 Oct.28.2004 page 662 of 1016
REJ09B0138-0600H
20.2 Register Descriptions
20.2.1 System Clock Control Register (SCKCR)
Bit:76543210
PSTOP — — — — SCK2 SCK1 SCK0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W —/(R/W)* — — R/W R/W R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Description
Bit 7
PSTOP Normal Operation Sleep Mode
Software
Standby Mode
Hardware
Standby Mode
0 ø output (initial value) ø output Fixed high High impedance
1 Fixed high Fixed high Fixed high High impedance
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be
written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to this bit.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master.
Bit 2
SCK2
Bit 1
SCK1
Bit 0
SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value)
1 Medium-speed clock is ø/2
1 0 Medium-speed clock is ø/4
1 Medium-speed clock is ø/8
1 0 0 Medium-speed clock is ø/16
1 Medium-speed clock is ø/32
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