Datasheet

Rev.6.00 Oct.28.2004 page 661 of 1016
REJ09B0138-0600H
Section 20 Clock Pulse Generator
20.1 Overview
The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock,
and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a
bus master clock selection circuit.
20.1.1 Block Diagram
Figure 20-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Duty
adjustment
circuit
Oscillator
Medium-
speed
divider
System clock to ø pin Internal clock
to supporting
modules
Bus master clock
to CPU, DTC,
and DMAC
ø/2 to ø/32
SCK2 to SCK0
SCKCR
Bus master
clock
selection
circuit
Figure 20-1 Block Diagram of Clock Pulse Generator
20.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 20-1 shows the register configuration.
Table 20-1 Clock Pulse Generator Register
Name Abbreviation R/W Initial Value Address*
System clock control register SCKCR R/W H'00 H'FF3A
Note:* Lower 16 bits of the address.