Datasheet

Rev.6.00 Oct.28.2004 page 653 of 1016
REJ09B0138-0600H
CE
A
18
to A
0
I/O
7
to I/O
0
OE
WE
VIH
VIL
VIL
t
acc
t
oh
t
oh
t
acc
Address stable Address stable
Figure 19-57 Timing Waveforms for CE/OE Enable State Read
CE
A
18
to A
0
I/O
7
to I/O
0
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
Address stable Address stable
t
df
Figure 19-58 Timing Waveforms for CE/OE Clocked Read
19.22.5 Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data
transfers should be performed.
• A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be
written to the extra addresses.
• The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be
started but a programming error will occur.
• Memory address transfer is executed in the second cycle (figure 19-59). Do not perform transfer later than the second
cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming
operations cannot be carried out on address blocks that have already been programmed.
• Confirm normal end of auto-programming by checking I/O
6
. Alternatively, status read mode can also be used for this
purpose (the I/O
7
status polling pin is used to identify the end of an auto-program operation).
• Status polling I/O
6
and I/O
7
information is retained until the next command write. As long as the next command write
has not been performed, reading is possible by enabling CE and OE.