Datasheet

Rev.6.00 Oct.28.2004 page 631 of 1016
REJ09B0138-0600H
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers
(FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be
read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE Description
0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
(Initial value)
1 Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.16.6 RAM Emulation Register (RAMER)
Bit:76543210
— — — — RAMS RAM2 RAM1 RAM0
Initial value : 0 0 0 0 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory
programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode. RAMER settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 19-34. To ensure correct operation of the emulation function, the ROM
for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal
execution of an access immediately after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS =
1, all flash memory blocks are program/erase-protected.
Bit 3
RAMS Description
0 Emulation not selected (Initial value)
Program/erase-protection of all flash memory blocks is disabled
1 Emulation selected
Program/erase-protection of all flash memory blocks is enabled