Datasheet

Rev.6.00 Oct.28.2004 page 34 of 1016
REJ09B0138-0600H
2.6.2 Instructions and Addressing Modes
Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use.
Table 2-2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function
Data
transfer
Arithmetic
operations
Instruction
MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — — — —
POP, PUSH — — ———— ——— — ———WL
LDM, STM — — ———— ——— — ———L
ADD, CMP BWL BWL ——————— —————
SUB WLBWL——————— —————
ADDX, SUBX B B ———— ——— — ————
ADDS, SUBS — L ——————— — ————
INC, DEC — BWL ———— ——— — ————
DAA, DAS — B ———— ——— — ————
NEG —BWL——————— — ————
EXTU, EXTS — WL ———— ——— — ————
TAS*
2
—— B —————— —————
Notes: 1. Cannot be used in the H8S/2357 Group.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
MOVFPE, — — —————B — —————
MOVTPE*
1
MULXU, — BW ——————— —————
DIVXU
MULXS, — BW ——————— —————
DIVXS
#xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 —
Logic
operations
System
control
Block data transfer
Shift
Bit manipulation
Branch
AND, OR, BWL BWL ——————— —————
XOR
ANDC, B — ——————— — ————
ORC, XORC
Bcc, BSR — — ———— ——— — ——
JMP, JSR — — —————— ——— —
RTS —— ——————— ————
TRAPA — — ———— ——— — ———
RTE —— ——————— ————
SLEEP — — ——————— — ———
LDC B B WWWW —W— W————
STC —B WWWW —W— W————
NOT —BWL———— ——— — ————
—BWL——————— — ————
—B B ———BB — B ————
NOP —— ———— ——— — ———
—— ———— ——— — ———BW
Legend:
B: Byte
W: Word
L: Longword