Datasheet

Rev.6.00 Oct.28.2004 page 33 of 1016
REJ09B0138-0600H
2.6 Instruction Set
2.6.1 Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1.
Table 2-1 Instruction Classification
Function Instructions Size Types
Data transfer MOV BWL 5
POP*
1
, PUSH*
1
WL
LDM, STM L
MOVFPE, MOVTPE*
3
B
Arithmetic ADD, SUB, CMP, NEG BWL 19
operations
ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS BW
EXTU, EXTS WL
TAS*
4
B
Logic operations AND, OR, XOR, NOT BWL 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B14
Branch Bcc*
2
, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1
Total: 65
Legend:
B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and
PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in the H8S/2357 Group.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.