Datasheet

Rev.6.00 Oct.28.2004 page 518 of 1016
REJ09B0138-0600H
15.1.2 Block Diagram
Figure 15-1 shows a block diagram of the Smart Card interface.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SCMR
SSR
SCR
Transmission/
reception control
BRR
Baud rate
generator
Internal
data bus
RxD
TxD
SCK
Parity generation
Parity check
Clock
ø
ø/4
ø/16
ø/64
TXI
RXI
ERI
SMR
Legend:
SCMR:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Smart Card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Figure 15-1 Block Diagram of Smart Card Interface
15.1.3 Pin Configuration
Table 15-1 shows the Smart Card interface pin configuration.
Table 15-1 Smart Card Interface Pins
Channel Pin Name Symbol I/O Function
0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output
Receive data pin 0 RxD0 Input SCI0 receive data input
Transmit data pin 0 TxD0 Output SCI0 transmit data output
1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output
Receive data pin 1 RxD1 Input SCI1 receive data input
Transmit data pin 1 TxD1 Output SCI1 transmit data output
2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output
Receive data pin 2 RxD2 Input SCI2 receive data input
Transmit data pin 2 TxD2 Output SCI2 transmit data output