Datasheet
Rev.6.00 Oct.28.2004 page 513 of 1016
REJ09B0138-0600H
Table 14-12 SCI Interrupt Sources
Channel
Interrupt
Source Description
DTC
Activation
DMAC
Activation Priority*
0 ERI Interrupt due to receive error
(ORER, FER, or PER)
Not
possible
Not
possible
High
RXI Interrupt due to receive data full
state (RDRF)
Possible Possible
TXI Interrupt due to transmit data empty
state (TDRE)
Possible Possible
TEI Interrupt due to transmission end
(TEND)
Not
possible
Not
possible
1 ERI Interrupt due to receive error
(ORER, FER, or PER)
Not
possible
Not
possible
RXI Interrupt due to receive data full
state (RDRF)
Possible Possible
TXI Interrupt due to transmit data empty
state (TDRE)
Possible Possible
TEI Interrupt due to transmission end
(TEND)
Not
possible
Not
possible
2 ERI Interrupt due to receive error
(ORER, FER, or PER)
Not
possible
Not
possible
RXI Interrupt due to receive data full
state (RDRF)
Possible Not
possible
TXI Interrupt due to transmit data empty
state (TDRE)
Possible Not
possible
TEI Interrupt due to transmission end
(TEND)
Not
possible
Not
possible Low
Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by
means of ICR and IPR.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the
same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI
interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt
will not be accepted in this case.