Datasheet
Rev.6.00 Oct.28.2004 page 450 of 1016
REJ09B0138-0600H
12.6.3 Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a
compare match event occurs.
Figure 12-12 shows this operation.
ΓΈ
Address
TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N+1
Compare match signal
Prohibited
Figure 12-12 Contention between TCOR Write and Compare Match
12.6.4 Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the
output statuses set for compare match A and compare match B, as shown in table 12-4.
Table 12-4 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low