Datasheet

Rev.6.00 Oct.28.2004 page 449 of 1016
REJ09B0138-0600H
12.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write takes priority and the
counter is not incremented.
Figure 12-11 shows this operation.
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 12-11 Contention between TCNT Write and Increment