Datasheet
Rev.6.00 Oct.28.2004 page 448 of 1016
REJ09B0138-0600H
12.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit timer.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear takes priority, so that the
counter is cleared and the write is not performed.
Figure 12-10 shows this operation.
ΓΈ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12-10 Contention between TCNT Write and Clear