Datasheet

Rev.6.00 Oct.28.2004 page 437 of 1016
REJ09B0138-0600H
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)
TCORB0 TCORB1
Bit :1514131211109876543210
Initial value : 1 1 1 1111111111111
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so
they can be accessed together by word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag of
TCSR is set. Note, however, that comparison is disabled during the T
2
state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and
OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1)
Bit:76543210
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at which TCNT is cleared,
and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 12.3, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled
or disabled when the CMFB flag of TCSR is set to 1.
Bit 7
CMIEB Description
0 CMFB interrupt requests (CMIB) are disabled (Initial value)
1 CMFB interrupt requests (CMIB) are enabled
Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled
or disabled when the CMFA flag of TCSR is set to 1.
Bit 6
CMIEA Description
0 CMFA interrupt requests (CMIA) are disabled (Initial value)
1 CMFA interrupt requests (CMIA) are enabled