Datasheet

Rev.6.00 Oct.28.2004 page 416 of 1016
REJ09B0138-0600H
11.2.2 Output Data Registers H and L (PODRH, PODRL)
PODRH
Bit:76543210
POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
PODRL
Bit:76543210
POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output.
11.2.3 Next Data Registers H and L (NDRH, NDRL)
NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the
contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare
match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups
have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.
NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in
software standby mode.
11.2.4 Notes on NDR Access
The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or
different output triggers.
Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event,
the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FF4E
consists entirely of reserved bits that cannot be modified and are always read as 1.
Address H'FF4C
Bit:76543210
NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W