Datasheet

Rev.6.00 Oct.28.2004 page 408 of 1016
REJ09B0138-0600H
Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T
2
state of
a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed.
Figure 10-55 shows the timing in this case.
Input capture
signal
Write signal
Address
ø
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10-55 Contention between Buffer Register Write and Input Capture
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur
simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is
set in TGR.
Counter
clear signal
TCNT input
clock
ø
TCNT
TGF
Prohibited
TCFV
H'FFFF H'0000
Figure 10-56 Contention between Overflow and Counter Clearing