Datasheet

Rev.6.00 Oct.28.2004 page 407 of 1016
REJ09B0138-0600H
Contention between TGR Read and Input Capture: If the input capture signal is generated in the T
1
state of a TGR
read cycle, the data that is read will be the data after input capture transfer.
Figure 10-53 shows the timing in this case.
Input capture
signal
Read signal
Address
ø
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 10-53 Contention between TGR Read and Input Capture
Contention between TGR Write and Input Capture: If the input capture signal is generated in the T
2
state of a TGR
write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Figure 10-54 shows the timing in this case.
Input capture
signal
Write signal
Address
ø
TCNT
TGR write cycle
T
1
T
2
M
TGR
M
TGR address
Figure 10-54 Contention between TGR Write and Input Capture