Datasheet

Rev.6.00 Oct.28.2004 page 406 of 1016
REJ09B0138-0600H
Contention between TGR Write and Compare Match: If a compare match occurs in the T
2
state of a TGR write cycle,
the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the
same value as before is written.
Figure 10-51 shows the timing in this case.
Compare
match signal
Write signal
Address
ø
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N+1
Prohibited
Figure 10-51 Contention between TGR Write and Compare Match
Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T
2
state of a TGR
write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write.
Figure 10-52 shows the timing in this case.
Compare
match signal
Write signal
Address
ø
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 10-52 Contention between Buffer Register Write and Compare Match