Datasheet

Rev.6.00 Oct.28.2004 page 405 of 1016
REJ09B0138-0600H
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T
2
state of a
TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed.
Figure 10-49 shows the timing in this case.
Counter clear
signal
Write signal
Address
ø
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 10-49 Contention between TCNT Write and Clear Operations
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T
2
state of a TCNT write
cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10-50 shows the timing in this case.
TCNT input
clock
Write signal
Address
ø
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 10-50 Contention between TCNT Write and Increment Operations