Datasheet

Rev.6.00 Oct.28.2004 page 403 of 1016
REJ09B0138-0600H
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC
or DMAC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the
CPU, and figure 10-47 shows the timing for status flag clearing by the DTC or DMAC.
Status flag
Write signal
Address
ø
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
Figure 10-46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
ø
Source address
DTC/DMAC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC/DMAC
write cycle
Figure 10-47 Timing for Status Flag Clearing by DTC/DMAC Activation