Datasheet

Rev.6.00 Oct.28.2004 page 398 of 1016
REJ09B0138-0600H
Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR
match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the
output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare
match signal is not generated until the TCNT input clock is generated.
Figure 10-36 shows output compare output timing.
TGR
TCNT
TCNT
input clock
ø
N
N N+1
Compare
match signal
TIOC pin
Figure 10-36 Output Compare Output Timing
Input Capture Signal Timing: Figure 10-37 shows input capture signal timing.
TCNT
Input capture
input
ø
N N+1 N+2
N
N+2
TGR
Input capture
signal
Figure 10-37 Input Capture Input Signal Timing
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter
clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input
capture occurrence is specified.