Datasheet

Rev.6.00 Oct.28.2004 page 382 of 1016
REJ09B0138-0600H
10.4.5 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as
set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10-6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates
independently in phase counting mode.
Table 10-6 Cascaded Combinations
Combination Upper 16 Bits Lower 16 Bits
Channels 1 and 2 TCNT1 TCNT2
Channels 4 and 5 TCNT4 TCNT5
Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the setting procedure for
cascaded operation.
Set cascading
Cascaded operation
Start count
<Cascaded operation>
[1]
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B’111 to select TCNT2
(TCNT5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Figure 10-21 Cascaded Operation Setting Procedure