Datasheet

Rev.6.00 Oct.28.2004 page 359 of 1016
REJ09B0138-0600H
Channel
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0 Description
3 0000TGR3A is Output disabled (Initial value)
1
1
0
1
output
compare
register
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR3A is
input
capture
register
Capture input
source is
TIOCA3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down
×: Don’t care
Channel
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0 Description
3 0000TGR3C is Output disabled (Initial value)
1
1
0
1
output
compare
register*
1
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR3C is
input
capture
register*
Capture input
source is
TIOCC3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down
×: Don’t care
Note: * When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.