Datasheet

Rev.6.00 Oct.28.2004 page 357 of 1016
REJ09B0138-0600H
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)
I/O Control C3 to C0 (IOC3 to IOC0):
IOA3 to IOA0 specify the function of TGRA.
IOC3 to IOC0 specify the function of TGRC.
Channel
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0 Description
0 0000TGR0A is Output disabled (Initial value)
1
1
0
1
output
compare
register
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR0A is
input
capture
register
Capture input
source is
TIOCA0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
1/ count clock
Input capture at TCNT1
count-up/count-down
×: Don’t care
Channel
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0 Description
0 0000TGR0C is Output disabled (Initial value)
1
1
0
1
output
compare
register*
1
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR0C is
input
capture
register*
Capture input
source is
TIOCC0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
1/count clock
Input capture at TCNT1
count-up/count-down
×: Don’t care
Note: * When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.