Datasheet

Rev.6.00 Oct.28.2004 page 355 of 1016
REJ09B0138-0600H
Channel
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0 Description
3 0000TGR3D is Output disabled (Initial value)
1
1
0
1
output
compare
register*
2
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR3D is
input
capture
register*
2
Capture input
source is
TIOCD3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down*
1
×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is
invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.