Datasheet
Rev.6.00 Oct.28.2004 page 354 of 1016
REJ09B0138-0600H
Channel
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0 Description
2 0000TGR2B is Output disabled (Initial value)
1
1
0
1
output
compare
register
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
1 × 0
1
0
1
×
TGR2B is
input
capture
register
Capture input
source is
TIOCB2 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
×: Don’t care
Channel
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0 Description
3 0000TGR3B is Output disabled (Initial value)
1
1
0
1
output
compare
register
Initial output is 0
output
0 output at compare match
1 output at compare match
Toggle output at compare
match
1 0 0 Output disabled
1 Initial output is 1 0 output at compare match
10
output
1 output at compare match
1 Toggle output at compare
match
100
1
0
1
×
TGR3B is
input
capture
register
Capture input
source is
TIOCB3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1 ×× Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down*
×: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is
invalid and input capture is not generated.