Datasheet

Rev.6.00 Oct.28.2004 page 351 of 1016
REJ09B0138-0600H
10.2.3 Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Channel 3: TIOR3H
Channel 4: TIOR4
Channel 5: TIOR5
Bit:76543210
IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Channel 0: TIOR0L
Channel 3: TIOR3L
Bit:76543210
IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in
hardware standby mode.
Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the
counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which
the counter is cleared to 0 is specified.