Datasheet

Rev.6.00 Oct.28.2004 page 349 of 1016
REJ09B0138-0600H
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0 Description
4000Internal clock: counts on ø/1 (Initial value)
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on ø/1024
1 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0 Description
5000Internal clock: counts on ø/1 (Initial value)
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKC pin input
1 0 Internal clock: counts on ø/256
1 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
10.2.2 Timer Mode Register (TMDR)
Channel 0: TMDR0
Channel 3: TMDR3
Bit:76543210
— — BFB BFA MD3 MD2 MD1 MD0
Initial value : 1 1 0 0 0 0 0 0
R/W : — — R/W R/W R/W R/W R/W R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit:76543210
— — — — MD3 MD2 MD1 MD0
Initial value : 1 1 0 0 0 0 0 0
R/W : — — — — R/W R/W R/W R/W