Datasheet

Rev.6.00 Oct.28.2004 page 343 of 1016

REJ09B0138-0600H

10.1.4 Register Configuration

Table 10-3 summarizes the TPU registers.

Table 10-3 TPU Registers

Channel Name Abbreviation R/W Initial Value Address *

0 Timer control register 0 TCR0 R/W H'00 H'FFD0

Timer mode register 0 TMDR0 R/W H'C0 H'FFD1

Timer I/O control register 0H TIOR0H R/W H'00 H'FFD2

Timer I/O control register 0L TIOR0L R/W H'00 H'FFD3

Timer interrupt enable register 0 TIER0 R/W H'40 H'FFD4

Timer status register 0 TSR0 R/(W)*

H'C0 H'FFD5

Timer counter 0 TCNT0 R/W H'0000 H'FFD6

Timer general register 0A TGR0A R/W H'FFFF H'FFD8

Timer general register 0B TGR0B R/W H'FFFF H'FFDA

Timer general register 0C TGR0C R/W H'FFFF H'FFDC

Timer general register 0D TGR0D R/W H'FFFF H'FFDE

1 Timer control register 1 TCR1 R/W H'00 H'FFE0

Timer mode register 1 TMDR1 R/W H'C0 H'FFE1

Timer I/O control register 1 TIOR1 R/W H'00 H'FFE2

Timer interrupt enable register 1 TIER1 R/W H'40 H'FFE4

Timer status register 1 TSR1 R/(W) *

H'C0 H'FFE5

Timer counter 1 TCNT1 R/W H'0000 H'FFE6

Timer general register 1A TGR1A R/W H'FFFF H'FFE8

Timer general register 1B TGR1B R/W H'FFFF H'FFEA

2 Timer control register 2 TCR2 R/W H'00 H'FFF0

Timer mode register 2 TMDR2 R/W H'C0 H'FFF1

Timer I/O control register 2 TIOR2 R/W H'00 H'FFF2

Timer interrupt enable register 2 TIER2 R/W H'40 H'FFF4

Timer status register 2 TSR2 R/(W) *

H'C0 H'FFF5

Timer counter 2 TCNT2 R/W H'0000 H'FFF6

Timer general register 2A TGR2A R/W H'FFFF H'FFF8

Timer general register 2B TGR2B R/W H'FFFF H'FFFA